The present technology relates to a clock tree unit cell circuit, a clock tree, and an apparatus.
From the past, a clock tree formed by connecting a plurality of inverters in cascade has been widely used in a semiconductor circuit. In such a clock tree, each of the inverters successively propagates a clock signal in a subsequent stage with a predetermined output delay time. The clock signal through which any appropriate connection point of a plurality of connection points formed between the plurality of inverters is propagated is obtained as a clock signal supplied to other circuits.
However, during a period where the clock signal is not supplied to the clock tree, a different logic state persists between the inverters in odd-number stages and the inverters in even-number stages, thereby generating a difference in a degree of deterioration of a transistor between the inverters in odd-number stages and the inverters in even-number stages. Therefore, when supply of the clock signal to the clock tree is resumed, the output delay time is different between the inverters in odd-number stages and the inverters in even-number stages.
This may result in changing (degrading) a duty ratio of the clock signal passing through the clock tree. Further, large deterioration of the transistor, a long clock tree, and a high clock frequency may cause a largely varied duty ratio and lose the clock signal itself.
In view of the above circumstances, Japanese Patent Application Laid-open No. 2006-33058 (hereinafter, referred to as Patent Document 1) discloses a clock tree using NAND instead of an inverter.
The technology disclosed in Patent Document 1 has a configuration so that a standby signal is inputted to the NAND at standby and has a merit that an inversion layer is not formed in MOS at standby to which a clock signal is inputted. Therefore, deterioration of the transistor, which is called negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI), can be prevented.